Mobile devices typically include a system-on-a-chip (SOC) that is packaged with one or more dynamic random access memories (DRAMs). To save power, various low power double data rate (LPDDR) protocols have been developed for the signaling between the SOC and the corresponding DRAMs. Depending upon the LPDDR mode of operation, the logic-high output voltage (Voh) used to transmit a binary one bit between the SOC and the DRAM is varied. This variation in the logic-high output voltage is independent of the power supply voltage (VDD) for the SOC. The resulting independence between the SOC power supply voltage and the logic-high output voltage for the data transmitted to each DRAM from the SOC causes issues for the SOC transmitter. In particular, the SOC transmitter typically is formed using an inverter that has a PMOS transistor in series with an NMOS transistor. As the output voltage varies depending upon the DRAM mode of operation, the NMOS transistor may transition from saturation to a triode mode of operation that makes impedance matching the SOC transmitter to the transmission line that propagates the data to each DRAM problematic.
Accordingly, there is a need in the art for transmitters having constant impedance while supporting variable logic-high output voltages.